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| d a t a sh eet preliminary speci?cation file under integrated circuits, ic22 1999 sep 27 integrated circuits SAA8113HL digital pc-camera signal processor
1999 sep 27 2 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL contents 1 features 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 black offset preprocessing 8.2 y, c r and c b separation 8.3 rgb processing 8.4 y processing 8.5 rgb to uv conversion 8.6 uv processing 8.7 display function 8.8 analog output processing 8.9 measurement engine 8.10 vh reference and window timing and control 8.11 pulse pattern generator 8.12 miscellaneous functions 8.13 mode control 8.14 microcontroller 8.15 audio amplifier 8.16 i 2 c-bus interface 9 limiting values 10 thermal characteristics 11 operating characteristics 12 electrical characteristics 13 application information 14 package outline 15 soldering 15.1 introduction to soldering surface mount packages 15.2 reflow soldering 15.3 wave soldering 15.4 manual soldering 15.5 suitability of surface mount ic packages for wave and reflow soldering methods 16 definitions 17 life support applications 18 purchase of philips i 2 c components 1999 sep 27 3 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 1 features high precision digital processing with 10-bit input medium resolution complementary mosaic ccd sensors pal or ntsc (interlaced mode only) internal ppg, dedicated to sharp, toshiba and panasonic sensors integrated microcontroller (80c51) for control loops auto optical black (aob), auto white balance (awb) and auto exposure (ae) black offset preprocessing rgb separation rgb processing (colour correction matrix, programmable knee and gamma) separate y-processing (saturation concealment, programmable knee and gamma) rgb to uv conversion (including down-sampling filters) noise reduction in y and uv display function for system evaluation analog output processing, including pal/ntsc encoder and 9-bit video digital-to-analog converter (vdac) measurement engine (prepared for ae and awb features) miscellaneous functions, e.g. power management, 7-bit control dac (cdac) serial interface with preprocessing vh reference and window timing for internal use master i 2 c-bus interface for communication with an external eeprom (containing the default settings) slave i 2 c-bus interface for communication with an external microcontroller parallel interface for communication with an external eprom (for rom code debugging) integrated audio amplifier. 2 applications low-cost desktop video applications videophone systems. 3 general description the SAA8113HL is a 2nd generation camera digital signal processor (dsp) designed for low-cost dtv applications. it integrates the dsp core, the pulse pattern generator (ppg), the 80c51 microcontroller and the vdac in one ic. it is the successor of the saa8110g, dedicated to analog output cameras. the SAA8113HL must be applied together with an analog front-end that includes a correlated double sampling (cds), an automatic gain control (agc) and an analog-to-digital converter (adc). this may be the tda8786 or the tda8784. the ppg generates the timing pulses to drive medium resolution pal/ntsc complementary mosaic ccd sensors (512 492 ntsc and 512 582 pal). the input of the dsp is 10 bits with a maximum pixel frequency equal to 9.66 mhz. the dsp core processes this sensor signal to a standard video output signal. the SAA8113HL output is an analog cvbs video signal. the microcontroller provides the settings for the ic registers from eeprom at power-up or reset and controls the awb, ae and aob loops. it also provides a hardware i 2 c-bus interface, so the microcontroller can be used as an i 2 c-bus slave. the software code is embedded in an internal rom but it is also possible to use a combined data and address bus, connected to an external program eprom. a built-in power management function allows the power dissipation to be optimized. 4 ordering information type number package name description version SAA8113HL lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1 1999 sep 27 4 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 5 quick reference data measured over full voltage and temperature range. note 1. this concerns pins scl and sda. symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.0 3.3 3.6 v i dd(tot) total supply current v ddd = 3.3 v - 60 - ma v i input voltage 3. 0v 1999 sep 27 6 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 7 pinning symbol pin i/o description m2 1 i test mode control signal bit 2 m1 2 i test mode control signal bit 1 m0 3 i test mode control signal bit 0 knob4 4 i input connected to dsp core knob3 5 i/o i/o connected to internal 80c51 knob2 6 i/o i/o connected to internal 80c51 knob1 7 i/o i/o connected to internal 80c51 knob0 8 i/o i/o connected to internal 80c51 reset 9 i power-on reset scle 10 o master i 2 c-bus clock output to control eeprom sdae 11 i/o master i 2 c-bus data i/o to control eeprom agnd1 12 i analog ground 1 for output buffers v dda1 13 i analog supply voltage 1 for output buffers scl 14 i slave i 2 c-bus clock input sda 15 i/o slave i 2 c-bus data i/o t1 16 i timer 1 for internal 80c51 v dda2 17 i analog supply voltage 2 for dac output buffer vdobcvbs 18 o vdac output buffer for cvbs signal agnd2 19 i analog ground 2 for dac output buffer agnd3 20 i analog ground 3 for analog dac core and band gap (connected to substrate) agnd4 21 i analog ground 4 for analog dac core and band gap (not connected to substrate) decref 22 o decoupled pin for reference voltage high v dda3 23 i analog supply voltage 3 for analog dac core and band gap miciab 24 i microphone input audio buffer v comab 25 i common voltage for audio buffer agnd5 26 i analog ground 5 for audio buffer (not connected to substrate) outab 27 o output audio buffer agnd6 28 i analog ground 6 for audio buffer (connected to substrate) v dda4 29 i analog supply voltage 4 for audio buffer outbven 30 o output to enable the bias voltage of the microphone for the audio buffer outgain 31 o output to control the gain factor of an external audio buffer psen 32 o program store enable; read strobe for external program memory (active low) ad8 33 o address bit 8 for external program memory (prom) ad9 34 o address bit 9 for external program memory (prom) ad10 35 o address bit 10 for external program memory (prom) ad11 36 o address bit 11 for external program memory (prom) ad12 37 o address bit 12 for external program memory (prom) ad13 38 o address bit 13 for external program memory (prom) ad14 39 o address bit 14 for external program memory (prom) v dda5 40 i analog supply voltage 5 for output buffers 1999 sep 27 7 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL agnd7 41 i analog ground 7 for output buffers p0.0 42 i/o port 0 bidirectional bit 0 for external program memory data i/o (prom) p0.1 43 i/o port 0 bidirectional bit 1 for external program memory data i/o (prom) p0.2 44 i/o port 0 bidirectional bit 2 for external program memory data i/o (prom) p0.3 45 i/o port 0 bidirectional bit 3 for external program memory data i/o (prom) p0.4 46 i/o port 0 bidirectional bit 4 for external program memory data i/o (prom) p0.5 47 i/o port 0 bidirectional bit 5 for external program memory data i/o (prom) p0.6 48 i/o port 0 bidirectional bit 6 for external program memory data i/o (prom) p0.7 49 i/o port 0 bidirectional bit 7 for external program memory data i/o (prom) ale 50 o address latch enable pulse for external latch led 51 o output to drive led ea 52 i external access select bit for internal 80c51 (active low) int1 53 i interrupt 1 for internal 80c51 dgnd1 54 i digital ground 1 for input buffers, predrivers and the digital core v ddd1 55 i digital supply voltage 1 for input buffers, predrivers and the digital core dgnd2 56 i digital ground 2 for input buffers, predrivers and the digital core v dda6 57 i analog supply voltage 6 for cdac rbiascdac 58 o bias resistor for cdac cdacout 59 o output cdac agnd8 60 i analog ground 8 for cdac agnd9 61 i analog ground 9 for 38 mhz (fundamental) crystal oscillator xin 62 i oscillator input xout 63 o oscillator output v dda7 64 i analog supply voltage 7 for 38 mhz (fundamental) crystal oscillator v1x 65 o vertical ccd transfer pulse 1x vh1x 66 o vertical ccd load pulse h1x v2x 67 o vertical ccd transfer pulse 2x v3x 68 o vertical ccd transfer pulse 3x vh3x 69 o vertical ccd load pulse h3x v4x 70 o vertical ccd transfer pulse 4x v dda8 71 i analog supply voltage 8 for output buffers agnd10 72 i analog ground 10 for output buffers ofdx 73 o over?ow drain pulse for shutter control fh2 74 o horizontal ccd transfer pulse f2 fh1 75 o horizontal ccd transfer pulse f1 fr 76 o ccd output ampli?er reset pulse (tda8786 or tda8784) fs 77 o ccd output level sample and hold pulse (tda8786 or tda8784) fcds 78 o reference level sample and hold pulse (tda8786 or tda8784) bcp 79 o black pixel clamp pulse (tda8786 or tda8784) dcp 80 o dummy pixel clamp pulse (tda8786 or tda8784) clk1 81 o pixel clock to preprocessor (tda8786 or tda8784) symbol pin i/o description 1999 sep 27 8 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL agnd11 82 i analog ground 11 for output buffers v dda9 83 i analog supply voltage 9 for output buffers smp 84 o switch mode pulse for dc-to-dc power supply ccd9 85 i (preprocessed) ad-converted ccd signal bit 9 ccd8 86 i (preprocessed) ad-converted ccd signal bit 8 ccd7 87 i (preprocessed) ad-converted ccd signal bit 7 ccd6 88 i (preprocessed) ad-converted ccd signal bit 6 ccd5 89 i (preprocessed) ad-converted ccd signal bit 5 ccd4 90 i (preprocessed) ad-converted ccd signal bit 4 ccd3 91 i (preprocessed) ad-converted ccd signal bit 3 ccd2 92 i (preprocessed) ad-converted ccd signal bit 2 ccd1 93 i (preprocessed) ad-converted ccd signal bit 1 ccd0 94 i (preprocessed) ad-converted ccd signal bit 0 dgnd3 95 i digital ground 3 for input buffers, predrivers and the digital core v ddd2 96 i digital supply voltage 2 for input buffers, predrivers and the digital core stdby 97 o standby control output to tda8786 or tda8784 strobe 98 o strobe to tda8786 or tda8784 sclk 99 o serial clock to tda8786 or tda8784 sdata 100 o serial data to tda8786 or tda8784 symbol pin i/o description 1999 sep 27 9 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 dcp bcp fcds fs fr fh1 fh2 ofdx agnd10 v dda8 v4x vh3x v3x v2x vh1x v1x v dda7 xout xin agnd9 agnd8 cdacout rbiascdac v dda6 dgnd2 v ddd1 dgnd1 int1 ea led m2 m1 m0 knob4 knob3 knob2 knob1 knob0 reset scle sdae agnd1 v dda1 scl sda t1 v dda2 vdobcvbs agnd2 agnd3 agnd4 decref v dda3 miciab v comab sdata sclk strobe stdby v ddd2 dgnd3 ccd0 ccd1 ccd2 ccd3 ccd4 ccd5 ccd6 ccd7 ccd8 ccd9 smp v dda9 agnd11 clk1 outgain ad8 ad9 ad10 ad11 ad12 ad13 ad14 v dda5 agnd7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ale agnd5 outab agnd6 v dda4 outbven 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SAA8113HL psen fce313 fig.2 pin configuration. 1999 sep 27 10 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 8 functional description 8.1 black offset preprocessing the ccd signal contains additional pixels outside the active window, which are used to measure the reference black level. these pixels are located in the optical black window, whose position can be set through the serial interface. the optical black level can be adjusted by the microcontroller in order to proceed rapidly. in this case, the microcontroller directly adjusts the analog preprocessing clamp included in the tda8786 or tda8784 and takes advantage of the full code range. otherwise, the black level is fixed by settings that are downloaded through the serial interface. 8.2 y, c r and c b separation for each pixel value, this block (see fig.3) generates the three components: the luminance signal y and the two colour signals c r (2r - g) and c b (2b - g). two line memories are required for this function. this block also provides vertical contour and white clip information. handbook, full pagewidth fce314 10 ccd inputs y c r c b white clip y vertical contour line memory line memory rgb colour separation fig.3 y, c r and c b separation diagram. 1999 sep 27 11 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 8.3 rgb processing the rgb processing (see fig.4) includes several features: colour space matrix to handle different types of colour sensors. the result is an optimum colour reproduction through the minimization of colour errors. the default matrix coefficients (positive or negative) can be adjusted through an external interface. separate and adjustable black offsets for r, g and b signals. separate gain controls for r and b signals dedicated to white balance control. the colour temperature can be adjusted independently of the colour matrix. knee function (compression factor and knee point are adjustable). adjustable gamma function to compensate for the non-linearity of display devices. the rgb path has a reduced bandwidth (less than 1 mhz), which is required for cvbs output. handbook, full pagewidth fce315 knee y r r gain r black lpf gamma + knee colour matrix c r g g black lpf gamma + knee c b b b gain b black lpf gamma + fig.4 rgb processing diagram. 1999 sep 27 12 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 8.4 y processing the separate y processing (see fig.5) includes the following features: saturation concealment to reduce the typical saturation distortion contour processing to improve picture sharpness noise reduction black offset pre-gain control to adjust the y signal with respect to the gamma range knee function (compression factor and knee point are adjustable) adjustable gamma function gain control. handbook, full pagewidth fce316 knee saturation concealment y y y pre-gain y black y vertical contour contour processing and noise reduction gamma y gain + + fig.5 y processing diagram. 8.5 rgb to uv conversion after r, g and b processing, the data path is converted to u and v signals (see fig.1). as a result of the reduced bandwidth, the y signal is only used as an input for control loop purposes (measurement engine). 8.6 uv processing the chrominance processing consists of a noise reduction by coring and the uv gain control. 8.7 display function as an optional feature and for software debugging, it is possible to visualize: eight display bars (assigned via the microcontroller) several measurement engine inputs. 1999 sep 27 13 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 8.8 analog output processing the analog output processing (see fig.6) contains a pal/ntsc encoder to transform the yuv data path to the cvbs output. the yuv input signals are up-sampled to twice the pixel clock and digitally prefiltered to keep the external analog filter simple. the block also contains an adjustable luminance clipper. handbook, full pagewidth fce317 u y v sync, blank, scaling, levels y vdobcvbs c pal/ntsc encoder mix vdac fig.6 analog output processing. 8.9 measurement engine the measurement engine performs data measurements on a field basis to get inputs for the ae and awb control loops of the microcontroller. up to 16 programmable windows can be used for the measurement. there are two down-samplers to prepare the data for two separate accumulators. it is possible to proceed with eight different measurements per field (odd and even fields separately). an internal ram workspace is used for data handling operation. 8.10 vh reference and window timing and control this block generates internal control signals for different purposes: vertical, horizontal and field references (v d ,h d and f i ) for pal or ntsc sensors specification of the active window and the optical black window specification of the measurement window grid with respect to the active window specification of the vertical position of the display bars, see section 8.7. all these specifications can be controlled through the serial interface. 1999 sep 27 14 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 8.11 pulse pattern generator the ppg generates timing pulses (figs. 7 to 10) for driving the ccd sensor (including the vertical driver) and pulses for the preprocessor tda8786 or tda8784 (correlated double sampling and black clamping). the ppg is dedicated to the medium resolution sensors with complementary mosaic colour filters (512 492 ntsc and 512 582 pal) described in table 1. figs. 11 and 12 show the ppg outputs. table 1 medium resolution ccd sensors driven by the internal ppg; note 1 note 1. all sensors are used with the vertical driver: nec m pd16510. the ppg includes special features: a charge reset is possible in every active line during the horizontal line blanking and multiple times during the vertical blanking a fast shutter interface is available. brand format type sharp pal 1/4 lz2423a ntsc 1/4 lz2413a pal 1/5 lz2523 ntsc 1/5 lz2513 toshiba pal 1/4 tcd5391ap ntsc 1/4 tcd5381ap sharp low voltage pal 1/4 lz2425 ntsc 1/4 lz2415 panasonic pal 1/4 mn37210fp pal 1/4 mn37201fp ntsc 1/4 mn37110fp ntsc 1/4 mn37101fp 1999 sep 27 15 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce318 fr_narrow_delayed fr_wide_delayed fr_narrow fr_wide fs_narrow fs_wide fcds fh2 fh1 xin 4 f pixel delay (typ. 7 ns) delay (typ. 7 ns) fig.7 high speed pulse timing (ccd sensor and preprocessor). 1999 sep 27 16 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce319 hd v1x v2x v3x v4x vh1x vh3x ntsc line 18 pal line 20 ntsc line 17 pal line 19 hd v1x v2x v3x v4x vh1x vh3x ntsc line 280 pal line 332 ntsc line 279 pal line 331 fig.8 sharp and toshiba ccd sensors/vertical drivers. 1999 sep 27 17 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce320 hd v1x v2x v3x v4x vh3x ntsc line 280 pal line 332 ntsc line 279 pal line 331 hd v1x v2x v3x v4x vh3x ntsc line 18 pal line 20 ntsc line 17 pal line 19 fig.9 sharp low-voltage ccd sensors/vertical drivers. 1999 sep 27 18 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce321 hd v1x v2x v3x v4x vh1x vh3x ofdx ntsc line 18 pal line 20 ntsc line 17 pal line 19 ntsc line 280 pal line 332 ntsc line 279 pal line 331 hd v1x v2x v3x v4x vh1x vh3x ofdx fig.10 panasonic ccd sensors/vertical drivers. 1999 sep 27 19 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce322 hd v1x v2x v3x v4x ofdx bcp dcp fig.11 sharp, all types, ppg output. handbook, full pagewidth fce323 hd v1x v2x v3x v4x ofdx bcp dcp fig.12 panasonic ppg output. 1999 sep 27 20 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 8.12 miscellaneous functions power consumption: it is possible to switch the dsp off without switching off the microcontroller. oscillator frequency: a 7-bit cdac tunes the oscillator frequency according to the external quartz frequency to guarantee the typical value of 38 mhz. the control digital value is downloaded through the serial interface. a 3-wire serial bus transfers the settings from the microcontroller to the preprocessor (tda8786 or tda8784). 8.13 mode control this block controls the operational modes of the SAA8113HL: application or test modes, see table 2. for a smooth adaptability, it is possible to bypass the main modules. table 2 mode control note 1. ea can be high or low, according to the application (high is for internal rom access, low for external access). m2 m1 m0 ea mode 000 ea; note 1 application mode 001 - application mode with bypassed ppg 010 - application mode with bypassed microcontroller 0 1 1 0 application mode with bypassed ppg and microcontroller 8.14 microcontroller the embedded microcontroller is basically an 80c654 core (80c51 family) with four ports. its functionality is standard, except that the core has no clock divided by 2 and the ports are dedicated input, output or i/o ports. ports p0 and p2 are available for connection to a debugger or to an external program eprom. the microcontroller controls the aob, the ae and the awb loops and downloads the settings for the dsp registers from eeprom at power-up or reset. table 3 lists the 80c51 standard function registers. the microcontroller includes the following features: 16 kbyte internal rom 256 byte ram hardware i 2 c-bus interface for communication with external microcontroller: sda and scl software i 2 c-bus interface for communication with external eeprom containing dsp settings: sdae and scle four i/o pins which can be used as human interface (knobs): p1.0, p1.1, p1.2 and p1.3. 1999 sep 27 21 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL table 3 80c51 standard function registers sfr name description sfr address data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 b b register f0h b7 b6 b5 b4 b3 b2 b1 b0 acc accumulator e0h acc7 acc6 acc5 acc4 acc3 acc2 acc1 acc0 siadr serial interface address dbh sa6 sa5 sa4 sa3 sa2 sa1 sa0 gc sidat serial interface data dah sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sista serial interface status d9h st7 st6 st5 st4 st3 0 0 0 sicon serial interface control d8h cr2 ens1 sta sto si aa cr1 cr0 psw program status word d0h cy ac f0 rs1 rs0 ov - p p4 port 4 c7h ------- stby ip interrupt priority b8h - ip6 ip5 ip4 pt1 px1 pt0 px0 p3 port 3 b0h rdn wrn t1 t0 int1 int0 fi crst ie interrupt enable a8h ea ie6 ie5 ie4 et1 ex1 et0 ex0 p2 port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 p1 port 1 90h sda scl sdae scle p1.3 p1.2 p1.1 p1.0 th1 timer high 1 8dh -------- th0 timer high 0 8ch -------- tl1 timer low 1 8bh -------- tl0 timer low 0 8ah -------- tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 tcon timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 pcon power control 87h ------ pd idl dph data pointer high 83h -------- dpl data pointer low 82h -------- sp stack pointer 81h sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 p0 port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 8.15 audio ampli?er an analog audio amplifier is integrated in the SAA8113HL. its gain can be adjusted between a high (45 db typical) and a low (13 db typical) value through the serial interface. 8.16 i 2 c-bus interface table 4 gives the command list of the i 2 c-bus interface. 1999 sep 27 22 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL table 4 command list add name function format range 0 control0 see table 5 for explanation byte n.a. 1 control1 see table 7 for explanation byte n.a. 2 control2 see table 8 for explanation byte n.a. 3 ob_startl_f0 ?rst line optical black window in ?eld 0 byte [0 to 255] 4 ob_startl_f1 ?rst line optical black window in ?eld 1 byte 256 + [0 to 255] 5 ob_startp ?rst pixel optical black window byte [0 to 255] 6 ob_pe_f0 ?xed optical black level for even pixel in ?eld 0 byte [0 to 127] 7 ob_po_f0 ?xed optical black level for odd pixel in ?eld 0 byte [0 to 127] 8 ob_pe_f1 ?xed optical black level for even pixel in ?eld 1 byte [0 to 127] 9 ob_po_f1 ?xed optical black level for odd pixel in ?eld 1 byte [0 to 127] 10 col_mat_p11 colour matrix coef?cient p11 byte [ - 128 to 127]/16 11 col_mat_p12 colour matrix coef?cient p12 byte [ - 128 to 127]/16 12 col_mat_p13 colour matrix coef?cient p13 byte [ - 128 to 127]/16 13 col_mat_p21 colour matrix coef?cient p21 byte [ - 128 to 127]/16 14 col_mat_p22 colour matrix coef?cient p22 byte [ - 128 to 127]/16 15 col_mat_p23 colour matrix coef?cient p23 byte [ - 128 to 127]/16 16 col_mat_p31 colour matrix coef?cient p31 byte [ - 128 to 127]/16 17 col_mat_p32 colour matrix coef?cient p32 byte [ - 128 to 127]/16 18 col_mat_p33 colour matrix coef?cient p33 byte [ - 128 to 127]/16 19 r_black ?xed r-black level offset byte [ - 128 to 127] 20 g_black ?xed g-black level offset byte [ - 128 to 127] 21 b_black ?xed b-black level offset byte [ - 128 to 127] 22 col_mat_rgain colour matrix r-gain factor byte [0 to 255]/128 23 col_mat_bgain colour matrix b-gain factor byte [0 to 255]/64 24 thr_lum threshold luminance for fader byte [0 to 255] 25 thr_color threshold colour for fader byte [0 to 255] 26 y_black ?xed y-black level offset byte [ - 128 to 127] 27 k1 gain correction for y path byte [0 to 255]/128 28 rgb_knee_offset offset for rgb knee byte [0 to 255] 29 y_knee_offset offset for y knee byte [0 to 255] 30 rgb_gamma_balance gamma multiplication factor (for rgb data path) 6 bits [0 to 63]/64 31 y_gamma_balance gamma multiplication factor (for y data path) 6 bits [0 to 63]/64 32 kcomb vertical contour comb ?lter coef?cient (ms) 4 bits [0 to 7]/8 vcgain vertical contour gain (ls) 4 bits [0 to 15]/16 33 cldlev contour level dependency level byte [0 to 255]/2 34 hclgain horizontal contour bpf low gain (ls) 4 bits [0 to 15]/16 hchgain horizontal contour bpf high gain (ms) 4 bits [0 to 15]/16 35 cnclev contour noise coring level 6 bits [0 to 63] 36 congain contour gain factor; see table 9 2 bits [0 to 63]/16 37 vu_value 1 length of vu_bar 1 byte 2 [0 to 255] 1999 sep 27 23 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 38 vu_value 2 length of vu_bar 2 byte 2 [0 to 255] 39 vu_value 3 length of vu_bar 3 byte 2 [0 to 255] 40 vu_value 4 length of vu_bar 4 byte 2 [0 to 255] 41 vu_value 5 length of vu_bar 5 byte 2 [0 to 255] 42 vu_value 6 length of vu_bar 6 byte 2 [0 to 255] 43 vu_value 7 length of vu_bar 7 byte 2 [0 to 255] 44 vu_value 8 length of vu_bar 8 byte 2 [0 to 255] 45 y_display_offset display offset (to be used with d_contour) byte 4 [0 to 255] 46 unclev u (chrominance) noise coring level byte [0 to 255]/4 47 vnclev v (chrominance) noise coring level byte [0 to 255]/4 48 ygain y (luminance) gain factor byte [0 to 255]/128 49 ugain u (b-y) gain factor byte [0 to 255]/128 50 vgain v (r-y) gain factor byte [0 to 255]/128 51 ctr_upd_line number of line for db-update control registers byte [0 to 255] 52 burst_level burst level colour burst byte [0 to 255] 53 a awb_a (measurement engine) byte [ - 128 to 127]/128 54 b awb_b (measurement engine) byte [ - 128 to 127]/128 55 c awb_c (measurement engine) byte [ - 128 to 127]/128 56 d awb_d (measurement engine) byte [ - 128 to 127]/128 57 e awb_e (measurement engine) 6 bits [0 to 63] 58 f awb_f (measurement engine) 6 bits [0 to 63] 59 highlightthr highlight threshold (measurement engine) byte [0 to 255] 60 me_resscale me sync + me result scale (me); see table 10 4 bits n.a. 61 disp_cntrl control bits for display function; see table 11 byte n.a. 62 ydisplev luminance display level in display function byte [0 to 255] 63 dmwsel display measurement window select; see table 13 byte n.a. 64 ana_whiteclip white clip limiter level for analog outputs byte 256 + [0 to 255] 65 pre_si_lsb control data for analog processing byte [0 to 255] 66 pre_si_msb control data and address for analog processing; see table 14 5 bits [0 to 63] 67 smp_cntrl control for switch mode power supply byte [0 to 255] 68 cdac_data cdac data (7-bit); see table 15 7 bits [0 to 127] 69 blanklev blanking level in analog output byte [0 to 255] 70 bl-setup setup level in analog output byte [0 to 255] 71 pre_proc_del control compensation delay w.r.t. preprocessing 4 bits [0 to 15] 72 bcp_start b clamp pulse start byte [0 to 255] 73 bcp_stop b clamp pulse stop byte [0 to 255] 74 dcp_start d clamp pulse start byte [0 to 255] 75 dcp_stop d clamp pulse stop byte [0 to 255] 76 ee_control_lsb e exposure lsb byte [0 to 255] add name function format range 1999 sep 27 24 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 77 ee_control_msb e exposure msb byte [0 to 255] 78 misc_control miscellaneous control bits; see table 16 5 bits [0 to 31] 79 fpix_act number of ?rst active pixel on a line byte [0 to 255] 80 lpix_act_lsb number of last active pixel on a line byte [0 to 255] 81 fline_act_f0 number of ?rst active line in ?eld 0 byte [0 to 255] 82 lline_act_f0 number of last active line in ?eld 0 byte [0 to 255] 83 fline_act_f1 number of ?rst active line in ?eld 1 byte [0 to 255] 84 lline_act_f1 number of last active line in ?eld 1 byte [0 to 255] 85 act_lines_msb msbs of active line numbers; see table 17 byte [0 to 255] 86 ppg_pol_sel select polarity of the ppg output signals; see table 18 5 bits n.a. 128 me_dpcc_a0_h_f1 me data path control code a 0_h ?eld 1 byte [0 to 255] 129 me_dpcc_a0_l_f1 me data path control code a 0_l ?eld 1 byte [0 to 255] 130 me_dpcc_b0_h_f1 me data path control code b 0_h ?eld 1 byte [0 to 255] 131 me_dpcc_b0_l_f1 me data path control code b 0_l ?eld 1 byte [0 to 255] 132 me_dpcc_a1_h_f1 me data path control code a 1_h ?eld 1 byte [0 to 255] 133 me_dpcc_a1_l_f1 me data path control code a 1_l ?eld 1 byte [0 to 255] 134 me_dpcc_b1_h_f1 me data path control code b 1_h ?eld 1 byte [0 to 255] 135 me_dpcc_b1_l_f1 me data path control code b 1_l ?eld 1 byte [0 to 255] 136 me_dpcc_a2_h_f1 me data path control code a 2_h ?eld 1 byte [0 to 255] 137 me_dpcc_a2_l_f1 me data path control code a 2_l ?eld 1 byte [0 to 255] 138 me_dpcc_b2_h_f1 me data path control code b 2_h ?eld 1 byte [0 to 255] 139 me_dpcc_b2_l_f1 me data path control code b 2_l ?eld 1 byte [0 to 255] 140 me_dpcc_a3_h_f1 me data path control code a 3_h ?eld 1 byte [0 to 255] 141 me_dpcc_a3_l_f1 me data path control code a 3_l ?eld 1 byte [0 to 255] 142 me_dpcc_b3_h_f1 me data path control code b 3_h ?eld 1 byte [0 to 255] 143 me_dpcc_b3_l_f1 me data path control code b 3_l ?eld 1 byte [0 to 255] 144 me_dpcc_a0_h_f2 me data path control code a 0_h ?eld 2 byte [0 to 255] 145 me_dpcc_a0_l_f2 me data path control code a 0_l ?eld 2 byte [0 to 255] 146 me_dpcc_b0_h_f2 me data path control code b 0_h ?eld 2 byte [0 to 255] 147 me_dpcc_b0_l_f2 me data path control code b 0_l ?eld 2 byte [0 to 255] 148 me_dpcc_a1_h_f2 me data path control code a 1_h ?eld 2 byte [0 to 255] 149 me_dpcc_a1_l_f2 me data path control code a 1_l ?eld 2 byte [0 to 255] 150 me_dpcc_b1_h_f2 me data path control code b 1_h ?eld 2 byte [0 to 255] 151 me_dpcc_b1_l_f2 me data path control code b 1_l ?eld 2 byte [0 to 255] 152 me_dpcc_a2_h_f2 me data path control code a 2_h ?eld 2 byte [0 to 255] 153 me_dpcc_a2_l_f2 me data path control code a 2_l ?eld 2 byte [0 to 255] 154 me_dpcc_b2_h_f2 me data path control code b 2_h ?eld 2 byte [0 to 255] 155 me_dpcc_b2_l_f2 me data path control code b 2_l ?eld 2 byte [0 to 255] 156 me_dpcc_a3_h_f2 me data path control code a 3_h ?eld 2 byte [0 to 255] 157 me_dpcc_a3_l_f2 me data path control code a 3_l ?eld 2 byte [0 to 255] add name function format range 1999 sep 27 25 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 158 me_dpcc_b3_h_f2 me data path control code b 3_h ?eld 2 byte [0 to 255] 159 me_dpcc_b3_l_f2 me data path control code b 3_l ?eld 2 byte [0 to 255] 160 me_res_a0_h me data path result accua 0_h byte [0 to 255] 161 me_res_a0_l me data path result accua 0_l byte [0 to 255] 162 me_res_b0_h me data path result accub 0_h byte [0 to 255] 163 me_res_b0_l me data path result accub 0_l byte [0 to 255] 164 me_res_a1_h me data path result accua 1_h byte [0 to 255] 165 me_res_a1_l me data path result accua 1_l byte [0 to 255] 166 me_res_b1_h me data path result accub 1_h byte [0 to 255] 167 me_res_b1_l me data path result accub 1_l byte [0 to 255] 168 me_res_a2_h me data path result accua 2_h byte [0 to 255] 169 me_res_a2_l me data path result accua 2_l byte [0 to 255] 170 me_res_b2_h me data path result accub 2_h byte [0 to 255] 171 me_res_b2_l me data path result accub 2_l byte [0 to 255] 172 me_res_a3_h me data path result accua 3_h byte [0 to 255] 173 me_res_a3_l me data path result accua 3_l byte [0 to 255] 174 me_res_b3_h me data path result accub 3_h byte [0 to 255] 175 me_res_b3_l me data path result accub 3_l byte [0 to 255] 176 me_subres_a0_h me data path sub-result accua 0_h byte [0 to 255] 177 me_subres_a0_l me data path sub-result accua 0_l byte [0 to 255] 178 me_subres_b0_h me data path sub-result accub 0_h byte [0 to 255] 179 me_subres_b0_l me data path sub-result accub 0_l byte [0 to 255] 180 me_subres_a1_h me data path sub-result accua 1_h byte [0 to 255] 181 me_subres_a1_l me data path sub-result accua 1_l byte [0 to 255] 182 me_subres_b1_h me data path sub-result accub 1_h byte [0 to 255] 183 me_subres_b1_l me data path sub-result accub 1_l byte [0 to 255] 184 me_subres_a2_h me data path sub-result accua 2_h byte [0 to 255] 185 me_subres_a2_l me data path sub-result accua 2_l byte [0 to 255] 186 me_subres_b2_h me data path sub-result accub 2_h byte [0 to 255] 187 me_subres_b2_l me data path sub-result accub 2_l byte [0 to 255] 188 me_subres_a3_h me data path sub-result accua 3_h byte [0 to 255] 189 me_subres_a3_l me data path sub-result accua 3_l byte [0 to 255] 190 me_subres_b3_h me data path sub-result accub 3_h byte [0 to 255] 191 me_subres_b3_l me data path sub-result accub 3_l byte [0 to 255] 192 me_win_start_0 simple window 0 (vstart, hstart) 4 bits [0 to 15] 193 me_win_stop_0 simple window 0 (vstop, hstop) 4 bits [0 to 15] 194 me_win_start_1 simple window 1 (vstart, hstart) 4 bits [0 to 15] 195 me_win_stop_1 simple window 1 (vstop, hstop) 4 bits [0 to 15] 196 me_win_start_2 simple window 2 (vstart, hstart) 4 bits [0 to 15] 197 me_win_stop_2 simple window 2 (vstop, hstop) 4 bits [0 to 15] 198 me_win_start_3 simple window 3 (vstart, hstart) 4 bits [0 to 15] add name function format range 1999 sep 27 26 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 199 me_win_stop_3 simple window 3 (vstop, hstop) 4 bits [0 to 15] 200 me_win_start_4 simple window 4 (vstart, hstart) 4 bits [0 to 15] 201 me_win_stop_4 simple window 4 (vstop, hstop) 4 bits [0 to 15] 202 me_win_start_5 simple window 5 (vstart, hstart) 4 bits [0 to 15] 203 me_win_stop_5 simple window 5 (vstop, hstop) 4 bits [0 to 15] 204 me_win_start_6 simple window 6 (vstart, hstart) 4 bits [0 to 15] 205 me_win_stop_6 simple window 6 (vstop, hstop) 4 bits [0 to 15] 206 me_win_start_7 simple window 7 (vstart, hstart) 4 bits [0 to 15] 207 me_win_stop_7 simple window 7 (vstop, hstop) 4 bits [0 to 15] 208 me_win_start_8 simple window 8 (vstart, hstart) 4 bits [0 to 15] 209 me_win_stop_8 simple window 8 (vstop, hstop) 4 bits [0 to 15] 210 me_win_start_9 simple window 9 (vstart, hstart) 4 bits [0 to 15] 211 me_win_stop_9 simple window 9 (vstop, hstop) 4 bits [0 to 15] 212 me_win_start_10 simple window 10 (vstart, hstart) 4 bits [0 to 15] 213 me_win_stop_10 simple window 10 (vstop, hstop) 4 bits [0 to 15] 214 me_win_start_11 simple window 11 (vstart, hstart) 4 bits [0 to 15] 215 me_win_stop_11 simple window 11 (vstop, hstop) 4 bits [0 to 15] 216 me_win_start_12 simple window 12 (vstart, hstart) 4 bits [0 to 15] 218 me_win_stop_12 simple window 12 (vstop, hstop) 4 bits [0 to 15] 219 me_win_start_13 simple window 13 (vstart, hstart) 4 bits [0 to 15] 220 me_win_stop_13 simple window 13 (vstop, hstop) 4 bits [0 to 15] 221 me_win_start_14 simple window 14 (vstart, hstart) 4 bits [0 to 15] 222 me_win_stop_14 simple window 14 (vstop, hstop) 4 bits [0 to 15] 223 me_ram_dummy_h dummy read/write (additional ram storage for 80c51) byte n.a. 224 me_ram_dummy_l dummy read/write (additional ram storage for 80c51) byte n.a. 225 highlightcount_h highlight counter h byte [0 to 255] 226 highlightcount_l highlight counter l byte [0 to 255] 227 awbcount_h awb counter h byte [0 to 255] 228 awbcount_l awb counter l byte [0 to 255] 229 me_ob_po_f0 measured optical black pixel odd ?eld 0; see table 19 byte [0 to 127] 230 me_ob_pe_f0 measured optical black pixel even ?eld 0; see table 20 byte [0 to 127] 231 me_ob_po_f1 measured optical black pixel odd ?eld 1; see table 21 byte [0 to 127] 232 me_ob_pe_f1 measured optical black pixel even ?eld 1; see table 22 byte [0 to 127] 254 dummy_read dummy read byte [0 to 255] 255 dummy_write dummy write byte [0 to 255] add name function format range 1999 sep 27 27 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL table 5 register details: address 0 control0 table 6 truth table for bits control0.1 and control0.2 table 7 register details: address 1 control1 table 8 register details: address 2 control2 bit name function control0.0 not used control0.1 rgb_knee_k compression factor for rgb_knee; see table 6 control0.2 rgb_knee_k compression factor for rgb_knee; see table 6 control0.3 pix_phase toggle phase for pixel in colour separation control0.4 line_phase toggle phase for line in colour separation control0.5 interline_phase toggle colour ?lter structure (interline) control0.6 not used control0.7 not used bit number compression factor 21 0 0 1/8 0 1 1/4 1 0 3/8 1 1 1/2 bit name function control1.0 fr_wide fr wide/narrow control1.1 fr_shift fr shifted/unshifted control1.2 fs_wide fs wide/narrow control1.3 dualpower sharp dual power/other sensor select control1.4 sharp sharp/panasonic sensor select control1.5 pal_ntsc choose between pal/ntsc control1.6 bcp_mode select bcp mode 1/0 control1.7 cp_toggle carrier phase toggle/not toggle bit name function control2.0 catch_ccd catch ccd data/normal operation control2.1 hfe_bypass high frequency enhancer bypass/active control2.2 y_test select y_test from rgb2(y)uv instead of y on/off control2.3 mod_bypass chrominance modulator bypass/active control2.4 double_c scale chrominance with factor 2 on/off control2.5 y_sel select as luminance input (f0) yae/y n control2.6 vcontour_lpf switch vertical contour lpf on/off control2.7 fader impl select fader implementation n1/n2 1999 sep 27 28 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL table 9 register details: address 36 congain table 10 register details: address 60 me_resscale table 11 register details: address 61 disp_cntrl table 12 truth table for bits disp_cntrl5 to disp_cntrl7] table 13 register details: address 63 dmwsel name function congain.0 to congain.5 contour gain factor (0 to 63/16) congain.6 contour gain fading off/on name function me_resscale.0 to me_resscale.2 me result scaler selection (0, 2, 4, 8 and 16) mecntrl.3 me synchronization (synchronize ?eld/frame toggle of measurement engine) name function disp_cntrl.0 and disp_cntrl.1 v display level disp_cntrl.2 and disp_cntrl.3 u display level disp_cntrl.4 contrast reduction/level insertion disp_cntrl.5 to disp_cntrl.7 display signal selection code; see table 12 bit number select code 765 0 0 0 no display 0 0 1 d_vu 0 1 0 d_wc 0 1 1 d_awbval 1 0 0 d_highlight 1 0 1 d_mwg 1 1 x d_contour name function dmwsel.0 display measurement window a for line 0 dmwsel.1 display measurement window b for line 0 dmwsel.2 display measurement window a for line 1 dmwsel.3 display measurement window b for line 1 dmwsel.4 display measurement window a for line 2 dmwsel.5 display measurement window b for line 2 dmwsel.6 display measurement window a for line 3 dmwsel.7 display measurement window b for line 3 1999 sep 27 29 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL table 14 register details: address 66 pre_si_msb table 15 register details: address 68 cdac_data table 16 register details: address 78 misc_control table 17 register details: address 85 act_lines_msb table 18 register details: address 86 ppg_pol_sel table 19 register details: address 229 me_ob_po_f0 name function pre_si_msb.0 and pre_si_msb.1 control data bits d8 and d9 pre_si_msb.2 to pre_si_msb.4 control address bits a0 to a2 name function cdac_data.0 to cdac_data.6 cdac data bits 0 to 6 name function misc_control.0 led off/on misc_control.1 audio on/off misc_control.2 audio gain low (13 db), high (45 db) misc_control.3 select 1 k w mode (output impedance) misc_control.4 standby on/off misc_control.5 to misc_control.7 reserved for miscellaneous additional functions name function act_lines_msb.0 and act_lines_msb.1 bits 8 and 9 for last active pixel number on a line act_lines_msb.2 and act_lines_msb.3 bits 8 and 9 for last active line number in ?eld 0 act_lines_msb.4 and act_lines_msb.5 bits 8 and 9 for ?rst active line number in ?eld 1/frame act_lines_msb.6 and act_lines_msb.7 bits 8 and 9 for last active line number in ?eld 1/frame name function ppg_pol_sel.0 select polarity of ppg output fr as inverted/non-inverted ppg_pol_sel.1 select polarity of ppg output fs as inverted/non-inverted ppg_pol_sel.2 select polarity of ppg output fcds as inverted/non-inverted ppg_pol_sel.3 select polarity of ppg output fh1 as inverted/non-inverted ppg_pol_sel.4 select polarity of ppg output fh2 as inverted/non-inverted name bit no function ccd_catch = 0 ccd_catch = 1 me_ob_po_f0.0 to me_ob_po_f0.6 me_ob_po_f00 to me_ob_po_f06 ccd2 to ccd8 me_ob_po_f0.7 0 ccd9 1999 sep 27 30 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL table 20 register details: address 230 me_ob_pe_f0 table 21 register details: address 231 me_ob_po_f1 table 22 register details: address 232 me_ob_pe_f1 9 limiting values in accordance with the absolute maximum rating system (iec 134); note 1 unless otherwise speci?ed. name bit no function ccd_catch = 0 ccd_catch = 1 me_ob_pe_f0.0 and me_ob_pe_f0.1 me_ob_pe_f00 and me_ob_pe_f01 ccd0 and ccd1 me_ob_pe_f0.2 to me_ob_pe_f0.6 me_ob_pe_f02 to me_ob_pe_f06 0 me_ob_pe_f0.7 knob4 name bit no function ccd_catch = 0 ccd_catch = 1 me_ob_po_f1.0 to me_ob_po_f1.6 me_ob_po_f16 to me_ob_po_f10 unde?ned me_ob_po_f1.7 0 name bit no function ccd_catch = 01 ccd_catch = 1 me_ob_pe_f1.0 to me_ob_pe_f1.6 me_ob_pe_f16 to me_ob_pe_f10 unde?ned me_ob_pe_f1.7 0 symbol parameter conditions min. max. unit v dddn digital supply voltages 1 and 2 for input buffer and pre-drivers - 0.5 +4.0 v v ddan analog supply voltages 1, 5, 8 and 9 for output buffers - 0.5 +4.0 v v dda2 analog supply voltage 2 for dac output buffer - 0.5 +4.0 v v dda3 analog supply voltage 3 for analog dac core and band gap - 0.5 +4.0 v v dda4 analog supply voltage 4 for audio buffer - 0.5 +4.0 v v dda6 analog supply voltage 6 for cdac - 0.5 +4.0 v v dda7 analog supply voltage 7 for 38 mhz crystal oscillator - 0.5 +4.0 v dgndn digital grounds 1, 2, and 3 for input buffer and predrivers - 0.5 +4.0 v agndn analog grounds 1, 7, 10 and 11 for output buffers - 0.5 +4.0 v agnd2 analog ground 2 for dac output buffer - 0.5 +4.0 v agnd3 analog ground 3 for analog dac core and band gap, connected to substrate - 0.5 +4.0 v agnd4 analog ground 4 for analog dac core and band gap, not connected to substrate - 0.5 +4.0 v agnd6 analog ground 6 for audio buffer connected to substrate - 0.5 +4.0 v agnd5 analog ground 5 for audio buffer not connected to substrate - 0.5 +4.0 v agnd8 analog ground 8 for cdac - 0.5 +4.0 v agnd9 analog ground 9 for 38 mhz crystal oscillator - 0.5 +4.0 v 1999 sep 27 31 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL notes 1. stress beyond these levels may cause permanent damage to the device. 2. for 5 v-tolerant buffers. 10 thermal characteristics 11 operating characteristics v ddd =v dda = 3.3 v 10%; t amb =0to70 c; unless otherwise speci?ed. v i , v o input or output voltage - 0.5 v dd + 0.5 v note 2 - 0.5 +5.5 v t stg storage temperature - 55 +150 c t amb ambient temperature 0 70 c t j junction temperature - 40 +125 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 56 k/w symbol parameter conditions min. typ. max. unit general supplies v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.0 3.3 3.6 v dgnd digital ground - 0.3 0.0 +0.3 v agnd analog ground - 0.3 0.0 +0.3 v i ddd digital supply current t amb =25 c - 45 - ma i dda analog supply current t amb =25 c - 15 - ma t amb ambient temperature 0 25 70 c data and control inputs or i/os (ccd9 to ccd0, m2 to m0, knob4 to knob0, reset, ea, t1, int1 and p0.7 to p0.0) v il low-level input voltage -- 0.2v ddd v v ih high-level input voltage 0.8v ddd -- v data and control outputs or i/os (smp, led, outbven, outgain, sdata, sclk, sdae, scle, strobe, stndby, fr, ofdx, ad14 to ad8 and p0.7 to p0.0) v ol low-level output voltage 0 - 0.4 v v oh high-level output voltage 0.85v ddd - v ddd v control outputs (fh1, fh2, fs, fcds and clk1) v ol low-level output voltage note 1 -- 0.8 v v oh high-level output voltage note1 2.2 -- v control outputs (v1x, v2x, v3x, v4x, vh1x and vh3x) v ol low-level output voltage notes 2 and 3 -- 0.8 v v oh high-level output voltage notes 2 and 3 2.6 -- v symbol parameter conditions min. max. unit 1999 sep 27 32 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL notes 1. connected to hct (lab resources) with v ih(min) = 2.0 v and v il(max) = 0.8 v. 2. connected to nec m pd16510 with v ih(min) = 0.8v dd and v il(max) = 0.3v dd . 3. connected to act/hct (lab resources) with v ih(min) = 2.0 v and v il(max) = 0.8 v. 12 electrical characteristics v ddd =v dda = 3.3 v 10%; t amb =0to70 c; unless otherwise speci?ed. control outputs (bcp and dcp) v ol low-level output voltage -- 0.6 v v oh high-level output voltage 2.2 -- v switch mode pulse for dc-to-dc power supply (smp) i o output current 3 -- ma output to drive the led (led) i o output current 5 -- ma symbol parameters conditions min. typ. max. unit cdac speci?cations l oad r l load resistance 10 -- k w c l load capacitance -- 100 pf t ransfer function v o dc output voltage at code 0 - 0.00 0.05 v dc output voltage at code 127 v ddd - 0.2 v ddd - 0.12 v ddd v res resolution - 7 - bit dnl differential non-linearity -- 1/2 lsb inl integral non-linearity -- 1 lsb cr conversion rate -- 60 hz b a analog bandwidth -- 60 hz r o output resistance - 13 -w s witching characteristics on rising full - scale step t pd propagation delay time to 50% value -- 75 ns t st1 settling time 10% to 90% full-scale -- 120 ns t st2 settling time to 1 lsb -- 156 ns symbol parameter conditions min. typ. max. unit 1999 sep 27 33 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL vdac speci?cations l oad r l load resistance with high impedance (1 k w mode) 0.8 1 - k w c l load capacitance with high impedance (1 k w mode) -- 5pf t ransfer function v o(0) dc output voltage at code 0 0.15 0.212 0.30 v v o(436) dc output voltage at code 436 1.45 1.55 1.75 v vrl (p-p) output voltage (436 to 0) (peak-to-peak value) note 1 1.15 1.288 1.6 v res resolution - 9 - bit dnl differential non-linearity -- 1 2 lsb inl integral non-linearity -- 1 lsb cr conversion rate - 19 - mhz f clk clock frequency - 19 - mhz b a analog bandwidth - 6.5 - mhz s/n signal-to-noise ratio dynamic 43 46 - db thd total harmonic distortion -- 50 - 42 db r o output resistance - 23 w s witching characteristics on rising full - scale step t pd propagation delay time to 50% value -- 13 ns t st1 settling time 10% to 90% full-scale -- 15 ns t st2 settling time to 1 lsb -- 50 ns audio ampli?er speci?cations l oad r l load resistance 5 -- k w c l load capacitance - 5 - pf t ransfer function v i(p-p) nominal input level (peak-to-peak value) - 5.6 - mv a1 ampli?cation at high level 43 44.8 47 db 141.2 173.7 223.8 a2 ampli?cation at low level 11 12.5 14 db 3.5 4.2 5.0 v oh(p-p) nominal output level at high level (peak-to-peak value) - 0.97 - v symbol parameters conditions min. typ. max. unit 1999 sep 27 34 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL v ol(rms) nominal output level at high level (rms value) - 0.34 - v v o2(p-p) nominal output level at low level (peak-to-peak value) - 23.5 - mv v o2(rms) nominal output level at low level (rms value) - 8.3 - mv v o(max)(p-p) maximum output level (peak-to-peak value) 2 -- v s/n signal-to-noise ratio 40 -- db thd total harmonic distortion at high level -- 60 - 50 db z i input impedance 5 -- k w z o output impedance -- 100 w b -3 db frequency range ( - 3 db) 0.1 - 20 khz b iassing i ref reference current - 25 -m a data input/output timing; (see fig.13) d ata inputs related to xin (ccd9 to ccd0 and knob4) t su(i)(d) data input setup time note 2 9.5 -- ns t h(i)(d) data input hold time note 2 10.5 -- ns d ata outputs related to xin (outbven, outgain, smp, led, sdata, sclk, strobe and stndby) t h(o)(d) data output delay time note 2 - 57ns t d(o)(d) data output hold time note 2 - 3 5.5 ns ppg high speed pulse timing; c l = 10 pf (see fig.14) t d1 fh2 fall time delay w.r.t. the rising edge of fh1 - 3 0 +3 ns t d2 fh2 rise time delay w.r.t. the falling edge of fh1 - 3 0 +3 ns t d3 fr fall time delay w.r.t. the rising edge of fh1 01 2ns t d3_delayed fr_delayed fall time delay w.r.t. the rising edge of fh1 7 8 10 ns t d4_wide fcds fall time delay w.r.t. the rising edge of fr_wide 12 3ns t d4_narrow fcds fall time delay w.r.t. the rising edge of fr_narrow 14 15 16 ns t d5 fh1 fall time delay w.r.t. the rising edge of fcds 01 2ns t d6_wide fh1 rise time delay w.r.t. the rising edge of fs_wide 01 2ns t d6_narrow fh1 rise time delay w.r.t. the rising edge of fs_narrow 14 15 16 ns t d7 clk1 fall time delay w.r.t. the rising edge of fh1 01 2ns symbol parameters conditions min. typ. max. unit 1999 sep 27 35 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL notes 1. full code swing of colour bar with maximum headroom of 16.4%. above code 436, the dac works but the settling time will decrease gradually. 2. the internal clock signal used in the dsp core is derived from xin: xin divided by 4. t d8 clk1 rise time delay w.r.t. the falling edge of fh1 01 2ns t wfh1 fh1 pulse width - 53 - ns t rfh1 fh1 rise time - 4 - ns t ffh1 fh1 fall time - 4 - ns t wfh2 fh2 pulse width - 53 - ns t rfh2 fh2 rise time - 4 - ns t ffh2 fh2 fall time - 4 - ns t wfr_wide fr_wide pulse width - 26 - ns t wfr_narrow fr_narrow pulse width - 13 - ns t rfr fr rise time - 4 - ns t ffr fr fall time - 4 - ns t wfcds fcds pulse width - 26 - ns t rfcds fcds rise time - 4 - ns t ffcds fcds fall time - 4 - ns t wfs_wide fs_wide pulse width - 40 - ns t wfs_narrow fs_narrow pulse width - 26 - ns t rfs fs rise time - 4 - ns t ffs fs fall time - 4 - ns t wclk1 clk1 pulse width - 53 - ns symbol parameters conditions min. typ. max. unit 1999 sep 27 36 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce324 t su(i)(d) t h(i)(d) t f t r 90% 90% t d(o)(d) 50% xin data input data output 10% 10% 10% 90% t h(o)(d) 10% 90% fig.13 data input/output timing. 1999 sep 27 37 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL handbook, full pagewidth fce325 clk1 fr_narrow_delayed fr_wide_delayed fr_narrow fr_wide fs_narrow fs_wide fcds fh2 fh1 t wfh1 t wfcds t wfh2 t d2 t d5 t d1 50% 50% 50% t wfs t d6_wide t d6_narrow 50% 50% 50% 50% 50% 50% 50% 50% 50% t wfr t wclk1 t d4_wide t d3 t d4_narrow t d7 t d3_delayed t d8 fig.14 ppg high speed pulse timing diagram. 1999 sep 27 38 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 13 application information handbook, full pagewidth fce326 analog (cvbs) program prom settings eeprom serial interface i 2 c-bus interface parallel interface human interface cdac micro- controller 80c51 vdac SAA8113HL digital signal processing preprocessing, timing and control sensor, timing and control drivers optics analog preprocessing ccd sensor pal/ntsc (medium resolution) cds, agc and adc mode control and clock generator lpf audio amplifier fig.15 application block diagram. 1999 sep 27 39 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 14 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 95-12-19 97-08-04 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1 1999 sep 27 40 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 15 soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 15.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1999 sep 27 41 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 15.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 1999 sep 27 42 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL 16 definitions 17 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 18 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1999 sep 27 43 philips semiconductors preliminary speci?cation digital pc-camera signal processor SAA8113HL notes ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 68 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 545006/25/01/pp 44 date of release: 1999 sep 27 document order number: 9397 750 04816 |
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